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PLL Design Jobs

Browse 16 PLL Design jobs on Inference Jobs.

16 jobs

4 wk. ago

Senior PLL Characterization Engineer

NVIDIA

Santa Clara, California, United States (On-site)$184–287.5K Yearly

Hardware Engineering

Test Engineering

PLL (Phase-Locked Loop)

ATE

3 wk. ago

Senior Characterization Engineer

NVIDIA

Santa Clara, California, United States (On-site)$184–287.5K Yearly

Characterization Engineer

Hardware Engineering

ATE Testing

PLL Characterization

3 wk. ago

Senior Mask Layout Design Engineer

NVIDIA

臺北市, Taipei, Taiwan (On-site)

Mask Layout Design

Analog/Mixed-Signal Layout Engineering

Cadence Virtuoso

Mixed Signal Circuit Design

2 wk. ago

SOC Clocks RTL Design Engineer

NVIDIA

Tel Aviv District, Israel (On-site)

2 wk. ago

Senior SOC Clocks RTL Design Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)

RTL Design

SOC Design Engineering

RTL Design

Verilog/SystemVerilog

19 hr. ago NVIDIA logo

Senior Mixed Signal Circuit Design Engineer

NVIDIA

Hsinchu, Taiwan, Taiwan (On-site)

Mixed Signal Design

Analog Circuit Design

Mixed Signal Circuit Design

Analog Circuit Design

5 days ago NVIDIA logo

Senior Mask Design Engineer - Hardware

NVIDIA

Santa Clara, California, United States (On-site)$132–207K Yearly

Mask Design Engineer

Physical Design Engineer

Cadence

CMOS

2 wk. ago

Physical Design Engineer, PnR

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly

Physical Design Engineer

PnR Engineer

Physical Design

Place and Route

3 wk. ago

D-

Analog Design Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155–250K Yearly

Analog Design

Mixed Signal Design

Analog Mixed Signal Design

Cadence

19 hr. ago d-Matrix logo

D-

Analog Design Engineer (L4/L5)

d-Matrix

Santa Clara, California, United States (Hybrid)$135–250K Yearly

Analog Design

Integrated Circuit Design

Analog Mixed Signal Design

Cadence

4 wk. ago

Senior Analog Layout Design Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)

Analog Layout

VLSI Design

Cadence Virtuoso

CMOS FinFET Technologies

4 wk. ago

Analog IC Design and Verification Engineer

Neuralink

Fremont, California, United States (On-site)$125–291K Yearly

Analog IC Design

Mixed Signal Design

CMOS Circuit Design

Mixed-Signal IC Design

5 days ago Tenstorrent logo

Analog Design Engineer

Tenstorrent

North America (Remote)$100–500K Yearly

Analog Design

Mixed Signal Design

Analog/Mixed-Signal IC Design

Die-to-die Chiplet PHY IP

4 wk. ago

Analog and Mixed-Signal IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35.00 Hourly

Analog and Mixed-Signal IC Design

ASIC Design

Analog and Mixed-Signal IC Design

CMOS Circuit Design

3 wk. ago

Cell Modeling and Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100–189.8K Yearly

Cell Modeling

Verification Engineering

Verilog HDL

SystemVerilog

4 wk. ago

Senior Analog and Mixed Signal Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168–264.5K Yearly

Analog Engineering

Mixed Signal Engineering

CMOS

PLL (Phase-Locked Loop)

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