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Analog Design Jobs in United States

Browse 25 Analog Design jobs in United States on Inference Jobs.

25 jobs

2 wk. ago

Analog IC Layout Engineer

Neuralink

South San Francisco, California, United States (On-site)$83–139K Yearly

Brain Interfaces Hardware

Analog IC Layout Engineering

Analog IC Layout

Mixed-Signal IC Layout

14 hr. ago d-Matrix logo

D-

Analog Design Engineer (L4/L5)

d-Matrix

Santa Clara, California, United States (Hybrid)$135–250K Yearly

Analog Design

Integrated Circuit Design

Analog Mixed Signal Design

Cadence

3 wk. ago

D-

Analog Design Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155–250K Yearly

Analog Design

Mixed Signal Design

Analog Mixed Signal Design

Cadence

4 wk. ago

Analog and Mixed-Signal IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35.00 Hourly

Analog and Mixed-Signal IC Design

ASIC Design

Analog and Mixed-Signal IC Design

CMOS Circuit Design

4 wk. ago

Analog IC Design and Verification Engineer

Neuralink

Fremont, California, United States (On-site)$125–291K Yearly

Analog IC Design

Mixed Signal Design

CMOS Circuit Design

Mixed-Signal IC Design

4 wk. ago

Senior Analog and Mixed Signal Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168–264.5K Yearly

Analog Engineering

Mixed Signal Engineering

CMOS

PLL (Phase-Locked Loop)

5 days ago NVIDIA logo

Senior Mixed Signal Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168–310.5K Yearly

5 days ago NVIDIA logo

Senior Circuit Design Engineer - Power

NVIDIA

Santa Clara, California, United States (Hybrid)$168–310.5K Yearly

Circuit Design

Power Electronics

Analog Circuit Design

Mixed Signal Circuit Design

4 days ago NVIDIA logo

Senior Circuit Design Engineer - Power Delivery

NVIDIA

Santa Clara, California, United States (Hybrid)$168–264.5K Yearly

Analog Design

Power Delivery Engineering

Analog Circuit Design

Mixed-Signal Design

4 wk. ago

Mixed Signal Design Validation Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168–310.5K Yearly

Mixed Signal Engineering

Hardware Validation

Python

Git

5 days ago NVIDIA logo

Senior Mask Design Engineer - Hardware

NVIDIA

Santa Clara, California, United States (On-site)$132–207K Yearly

Mask Design Engineer

Physical Design Engineer

Cadence

CMOS

3 wk. ago

Electrical Engineering Intern [Fall 2026]

Figure

San Jose, California, United States (On-site)$40.00 – $45.00 Hourly

Electrical Engineering

Hardware Engineering

PCB Design

Power Electronics

5 days ago NVIDIA logo

Senior PDK Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168–310.5K Yearly

Semiconductor Engineering

Electrical Engineering

PDK

VLSI Design

4 wk. ago

Senior GPU Low Power Architect

NVIDIA

Santa Clara, California, United States (On-site)$136–264.5K Yearly

Hardware Engineering

GPU Architecture

Low Power Architectures

2 wk. ago

Silicon Engineer

Anthropic

San Francisco, California, United States (Hybrid)$320–485K Yearly

Silicon Engineering

Hardware Engineering

Front-end Design

Pre-Silicon Verification

1 wk. ago

Electrical Engineer

Graphcore

Austin, Texas, United States (On-site)

HW Platform Dev.

Electrical Engineering

Schematic Capture

PCB Design

7 days ago Crusoe logo

Staff Hardware Systems Engineer

Crusoe

San Francisco, California, United States (On-site)$208–253K Yearly

Hardware Engineering

Hardware Systems Engineering

PCIe

InfiniBand

4 wk. ago

Electrical Engineer, Implant Embedded Systems

Neuralink

Austin, Texas, United States (On-site)$109.8–238.1K Yearly

Brain Interfaces Hardware

Electrical Engineering

PCB Design

3 wk. ago

D-

Technical Program Manager – Hardware/Silicon, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196–300K Yearly

Technical Program Management

Hardware Engineering

RTL Design

Design Verification

3 wk. ago

Senior Characterization Engineer

NVIDIA

Santa Clara, California, United States (On-site)$184–287.5K Yearly

Characterization Engineer

Hardware Engineering

ATE Testing

PLL Characterization

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