SystemVerilog salaries
Average salary
$141.5–298.9K/ year
25th percentile
$100K
Median
$203K
75th percentile
$310.5K
Based on
118 jobs
Salary by seniority
| Level | Average | Board baseline | vs. board |
|---|---|---|---|
| Entry level | $107.4–201.9K | $105.4–166K | +14% |
| Mid-level | $134.8–263.8K | $157–243.1K | +0% |
| Senior | $154.3–340.1K | $192.8–290.9K | +2% |
Top companies
Top locations
US
United States
107 jobs
$145.5–294.1K
CU
California, United States
75 jobs
$156.5–288.2K
SC
Santa Clara, CA, United States
55 jobs
$140.3–269.2K
TU
Texas, United States
23 jobs
$112.3–332.6K
AT
Austin, TX, United States
21 jobs
$113.5–316.6K
SF
San Francisco, CA, United States
7 jobs
$243.4–456.1K
SC
Sunnyvale, CA, United States
5 jobs
$226–272K
DN
Durham, NC, United States
4 jobs
$118–227.1K
NC
North Carolina, United States
4 jobs
$118–227.1K
SJ
San Jose, CA, United States
4 jobs
$150–275K
Top titles
Related skills
Frequently asked questions
- What is the average salary for SystemVerilog?
- The average salary for SystemVerilog is $141,494.00 – $298,913.00 per year, based on 118 job postings on this board that disclose pay.
- How is the salary figure for SystemVerilog calculated?
- These figures are aggregated from current and recent job postings on this board that disclose pay, then averaged across roles. They are estimates, not guarantees of compensation.