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Fusion Compiler Jobs

Browse 13 Fusion Compiler jobs on Inference Jobs.

13 jobs

5 days ago NVIDIA logo

Senior Physical Design Methodology Engineer, PPA Fusion Compiler

NVIDIA

Santa Clara, California, United States (On-site)$168–310.5K Yearly

Physical Design Engineering

Methodology Engineering

Physical Design

PPA

12 hr. ago NVIDIA logo

Senior Synthesis CAD Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)

Synthesis Engineering

CAD Engineering

Synthesis

Synopsys Fusion Compiler

2 wk. ago

Physical Design Engineer, PnR

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly

Physical Design Engineer

PnR Engineer

Physical Design

Place and Route

3 wk. ago

AI Silicon Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150–250K Yearly

Physical Design Engineering

Silicon Engineering

Physical Design

Physical Verification

3 wk. ago

Staff Engineer, ML Models

Tenstorrent

Cyprus (Hybrid)

Machine Learning Engineer

Staff Engineer

PyTorch

TensorFlow

2 wk. ago

Physical Design Engineer - Block Level, Subsystem Implementation

Etched

Austin, Texas, United States (On-site)

ASIC

Physical Design Engineer

Physical Design

GDSII

2 wk. ago

AI/ML Physical Design Flow Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100–500K Yearly

1 wk. ago

Physical Design Engineer, Synthesis and Implementation

NVIDIA

Westford, Massachusetts, United States (On-site)$116–218.5K Yearly

Physical Design Engineer

Synthesis Engineering

RTL-to-Gate Synthesis

QoR

3 wk. ago

Physical Design Engineer

Etched

San Jose, California, United States (On-site)$150–275K Yearly

Physical Design Engineering

ASIC Design

Physical Design

RTL Synthesis

3 wk. ago

Physical Design Engineer - Full Chip Implementation

Etched

San Jose, California, United States (On-site)

ASIC

Physical Design Engineering

Floorplanning

Place and Route

3 wk. ago

Physical Design Engineer

Etched

Austin, Texas, United States (On-site)$150–275K Yearly

ASIC Design

Physical Design Engineer

Physical Design

RTL Synthesis

3 wk. ago

Physical Design Engineer - Flow & Methodologies

Etched

San Jose, California, United States (On-site)

Physical Design Engineering

ASIC

RTL-to-GDSII Flow

Cadence Innovus

3 wk. ago

Physical Design Engineer - Block Level, Subsystem Implementation

Etched

San Jose, California, United States (On-site)

Physical Design Engineering

ASIC Design

RTL Synthesis

GDSII Sign-off

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