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EM/IR Analysis Jobs

Browse 16 EM/IR Analysis jobs on Inference Jobs.

16 jobs

1 mo. ago

Senior Memory Mask Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)

Memory Design Engineering

IC Layout Engineering

CMOS

Memory Layout

5 days ago NVIDIA logo

Senior Physical Design Methodology Engineer, PPA Fusion Compiler

NVIDIA

Santa Clara, California, United States (On-site)$168–310.5K Yearly

Physical Design Engineering

Methodology Engineering

Physical Design

PPA

3 wk. ago

Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$230–280K Yearly

Physical Design Engineering

ASIC Design

Physical Design

Physical Verification

3 wk. ago

Physical Design Signoff CAD Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)

Physical Design Engineering

CAD Engineering

Physical Design

STA

3 wk. ago

3D Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150–270K Yearly

3 wk. ago

AI Silicon Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150–250K Yearly

Physical Design Engineering

Silicon Engineering

Physical Design

Physical Verification

3 wk. ago

Physical Design Engineer (Bengaluru)

Cerebras

Bengaluru, Karnataka, India (On-site)

Physical Design Engineer

Silicon Engineering

Physical Design

Physical Verification

3 wk. ago

Senior Circuit Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)

Senior Circuit Design Engineer

Circuit Design Engineering

Circuit Design

Spice Simulations

2 wk. ago

Physical Design Engineer, PnR

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly

Physical Design Engineer

PnR Engineer

Physical Design

Place and Route

4 wk. ago

Manager, Physical Design Circuit and Signoff CAD

NVIDIA

Yokne'am, Northern District, Israel (On-site)

CAD Engineering Management

Physical Design

CAD

EDA

4 wk. ago

Senior Analog Layout Design Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)

Analog Layout

VLSI Design

Cadence Virtuoso

CMOS FinFET Technologies

3 wk. ago

Physical Design Engineer - Block Level, Subsystem Implementation

Etched

San Jose, California, United States (On-site)

Physical Design Engineering

ASIC Design

RTL Synthesis

GDSII Sign-off

1 day ago

Physical Design Engineer

Etched

Cupertino, California, United States (On-site)

Hardware

Physical Design

ASIC

4 wk. ago

Staff Technical Program Manager, Physical Engineering

Tenstorrent

Santa Clara, California, United States (Hybrid)$100–500K Yearly

Technical Program Management

Physical Engineering

Physical Design

Technical Program Management

2 wk. ago

AI Subsystems Physical Design Lead

Tenstorrent

Santa Clara, California, United States (Hybrid)$100–500K Yearly

Physical Design Engineer

ASIC Design

Physical Design

SoC Design

3 wk. ago

Physical Design Engineer - Flow & Methodologies

Etched

San Jose, California, United States (On-site)

Physical Design Engineering

ASIC

RTL-to-GDSII Flow

Cadence Innovus

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