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Semiconductor Layout Engineer

Semiconductor Layout Engineer Jobs

Browse 13 Semiconductor Layout Engineer jobs on Inference Jobs.

13 jobs

5 days ago NVIDIA logo

Senior Photonic Layout Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$132–235.8K Yearly

Photonic Layout Design Engineer

Silicon Photonics Engineer

Silicon Photonics

SerDes

4 wk. ago

CAD Layout Design Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)

3 wk. ago

Analog IC Layout Engineer

Neuralink

South San Francisco, California, United States (On-site)$83–139K Yearly

Brain Interfaces Hardware

Analog IC Layout Engineering

Analog IC Layout

Mixed-Signal IC Layout

2 wk. ago

Memory Mask Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)

Memory Design Engineering

IC Layout Engineering

CMOS

Cadence

2 days ago Etched logo

IC Package Engineer

Etched

Cupertino, California, United States (On-site)

Hardware Engineering

Semiconductor Engineering

CoWoS

Substrate Layout

5 days ago NVIDIA logo

Senior Mask Design Engineer – Hardware

NVIDIA

Bengaluru, Karnataka, India (On-site)

4 wk. ago

Senior SRAM Circuit Design Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)

SRAM Circuit Design

Digital IP Design

SRAM Circuit Design

Transistor Level Circuit Design

5 days ago NVIDIA logo

Senior PDK Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168–310.5K Yearly

Semiconductor Engineering

Electrical Engineering

PDK

VLSI Design

1 wk. ago

Senior Mask Design Engineer – Hardware

NVIDIA

United States (Remote)$136–258.8K Yearly

5 days ago NVIDIA logo

Senior ICV CAD Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168–264.5K Yearly

22 hr. ago d-Matrix logo

D-

Analog Design Engineer (L4/L5)

d-Matrix

Santa Clara, California, United States (Hybrid)$135–250K Yearly

Analog Design

Integrated Circuit Design

Analog Mixed Signal Design

Cadence

3 wk. ago

D-

Analog Design Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155–250K Yearly

Analog Design

Mixed Signal Design

Analog Mixed Signal Design

Cadence

2 wk. ago

Full-Chip Physical Design Verification Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100–500K Yearly

Physical Design Verification

SoC Tapeout Engineering

Physical Design Verification

DRC (Design Rule Check)