Jobs on Inference Jobs

Physical Design Methodology

GDSII

2 wk. ago

Physical Design Methodology Engineer, AI HW IP

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly

CAD Engineering

RTL-to-GDSII

FusionCompiler

2 days ago Etched logo

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)

2 wk. ago

Physical Design Engineer, PnR

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly

PnR Engineer

Low Power ASIC Engineering

Place and Route

5 days ago NVIDIA logo

Low Power ASIC Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100–189.8K Yearly

Low Power Design Verification

Low Power Design

GPU Architecture

2 days ago Etched logo

Physical Design Engineer

Etched

Cupertino, California, United States (On-site)

Hardware

ASIC

2 wk. ago

Digital Verification Engineer

Neuralink

South San Francisco, California, United States (On-site)$131–243K Yearly

ASIC Design Verification

Digital Verification

SystemVerilog

Python

4 days ago Tenstorrent logo

Physical Design Engineer, AI Accelerator IP

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly

VLSI Design

Synthesis

4 wk. ago

Senior GPU Low Power Architect

NVIDIA

Santa Clara, California, United States (On-site)$136–264.5K Yearly

Hardware Engineering

GPU Architecture

Low Power Architectures

3 wk. ago

Physical Design Engineer

Etched

San Jose, California, United States (On-site)$150–275K Yearly

ASIC Design

RTL Synthesis

3 wk. ago

Physical Design Engineer

Etched

Austin, Texas, United States (On-site)$150–275K Yearly

ASIC Design

Universal Verification Methodology (UVM)

RTL Synthesis

3 wk. ago

Senior ASIC Design Verification Engineer - LPU

NVIDIA

California, United States (Hybrid)$168–310.5K Yearly

ASIC Design Verification

Hardware Engineering

SystemVerilog

3 wk. ago

Physical Design Engineer - Flow & Methodologies

Etched

San Jose, California, United States (On-site)

ASIC

RTL-to-GDSII Flow

Cadence Innovus

3 wk. ago

Physical Design Engineer - Block Level, Subsystem Implementation

Etched

San Jose, California, United States (On-site)

ASIC Design

RTL Synthesis

GDSII Sign-off

1 mo. ago

Senior Physical Design Methodology Engineer, Innovus Flows

NVIDIA

US, CA, Santa Clara, United States of America (On-site)$168–310.5K Yearly

Methodology Engineer